1. Field of the Invention
The present invention relates in general to a decision directed carrier recovery circuit using a phase error detector, and more particularly to an improved phase error detector for a decision directed carrier recovery circuit which is mainly used in quadrature amplitude modulation (referred to hereinafter as QAM) of a digital transmission system.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a block diagram of a conventional decision directed carrier recovery circuit. As shown in this drawing, the conventional decision directed carrier recovery circuit comprises a demodulator 1 for adjusting a frequency and a phase of an input carrier to demodulate an original signal therefrom. The demodulator 1 includes a complex multiplier.
The conventional decision directed carrier recovery circuit also comprises a signal decision unit 2 for deciding an output signal [Re(q.sub.k),Im(q.sub.k)] from the demodulator 1 as a specified symbol, a phase error detector 3 for performing multiplication and division for the output signal [Re(q.sub.k),Im(q.sub.k)] from the demodulator 1 and an output signal [Re(A.sub.k),Im(A.sub.k)] from the signal decision unit 2 to detect a phase error therebetween, a loop filter 4 for low pass filtering an output signal from the phase error detector 3, and a voltage controlled oscillator (VCO) 5 for outputting an signal for the adjustment of the frequency and phase of the input carrier to the demodulator 1 in response to an output signal from the loop filter 4. Here, it can be seen that the components in FIG. 1 form a phase locked loop (PLL).
Referring to FIG. 4, there is shown a block diagram of the phase error detector 3 in FIG. 1. As shown in this drawing, the phase error detector 3 includes a numerator calculator 31 for receiving the output signal [Re(q.sub.k),Im(q.sub.k)] from the demodulator 1 and the output signal [Re(A.sub.k),Im(A.sub.k)] from the signal decision unit 2 and calculating a numerator of a phase error calculation expression, a first absolute value calculator 32 for calculating an absolute value of a component Im(A.sub.k) of the output signal from the signal decision unit 2, a second absolute value calculator 33 for calculating an absolute value of a component Re(A.sub.k) of the output signal from the signal decision unit 2, a multiplier 34 for multiplying an output value from the first absolute value calculator 32 by an output value from the second absolute value calculator 33, and a divider 35 for dividing an output value X from the numerator calculator 31 by an output value Y from the multiplier 34.
The operation of the conventional decision directed carrier recovery circuit with the above-mentioned construction will hereinafter be described with reference to FIGS. 2 and 3. FIG. 2 is a view illustrating a signal constellation of 32-QAM and FIG. 3 is a view illustrating the phase error between the signals A.sub.k and q.sub.k.
The signal demodulated by the demodulator 1 including the complex multiplier is decided as the specified symbol by the signal decision unit 2. The output signal from the signal decision unit 2 and the signal demodulated by the demodulator 1 are applied for calculation of the phase error in the phase error detector 3. The resultant signal from the phase error detector 3 is low pass filtered by the loop filter 4 and then applied to the VCO 5, which outputs the signal for the adjustment of the frequency and phase of the input carrier to the demodulator 1 in response to the output signal from the loop filter 4.
Because one of 32 or 2.sub.5 symbols is transmitted at a time in the 32-QAM as shown in FIG. 2, binary data is transmitted in the unit of 5 bits. The transmitted signal is rotated due to a variation in the frequency and phase resulting from a channel characteristic. A carrier recovery loop is required to compensate for such a rotation. A phase error resulting from the rotation can be obtained on the basis of the principle of FIG. 3. Namely, provided that the original signal A.sub.k is rotated to q.sub.k in the transmission as shown in FIG. 3, multiplication of a conjugate complex number A.sub.k * of the original signal A.sub.k and the rotated signal q.sub.k is .vertline.q.sub.k .vertline..vertline.A.sub.k .vertline. and the rotated angle is .phi.-.THETA.. Here, since .vertline.q.sub.k .vertline.=.vertline.A.sub.k .vertline., .vertline.q.sub.k .vertline..vertline.A.sub.k .vertline.=.vertline.A.sub.k .vertline..sup.2. Also, since the phase error .epsilon..sub.k =.phi.-.THETA., it can be expressed as follows: EQU .epsilon..sub.k =sin.sup.-1 [Im(q.sub.k .multidot.A.sub.k *) .vertline.A.sub.k .vertline..sup.2 ]
Provided that the phase error is very small, .epsilon..sub.k .apprxeq.sin.epsilon..sub.k. As a result, the phase error .epsilon..sub.k can be expressed as follows: EQU .epsilon..sub.k =[Im(q.sub.k .multidot.A.sub.k *)/.vertline.A.sub.k .vertline..sup.2 ]
However, the conventional phase error detector has a disadvantage in that the divider requires a number of logical elements to perform the division, resulting in an increase in the size and the cost. Also, much time required in the calculation results in a degradation in a performance of the phase locked loop.
On the other hand, a technique for detecting a phase error in a video display apparatus is shown in U.S. Pat. No. 5,184,091. This technique relates to tuning and control devices for a display scan system. In this technique, a control system is provided to allow an oscillator to operate on a broad range of frequency, to prevent generation of an error in frequency and phase of a signal from the oscillator with respect to a reference frequency. In this connection, the above technique does not relates to that to be proposed by the present invention.